Software-hardware co-design for energy-efficient neural network accelerators

Designing high-performance deep neural networks (DNNs) under hardware constraints is a challenging task due to the high computational cost of architecture evaluation and the complex interaction between neural architectures and hardware platforms. To address these challenges, this dissertation proposes an integrated research framework that spans algorithm-level network evaluation, hardware-aware optimisation, and cycle-accurate performance simulation. First, we introduce RBFleX-NAS, a novel zero-cost training-free neural architecture search (NAS) method that accurately estimates the relative performance of DNN architectures without any training. By leveraging Radial Basis Function-based local approximations, RBFleX-NAS significantly reduces the computational burden associated with conventional NAS methods. Next, we present H-RBFleX, a co-optimisation framework that integrates a precomputed monotonic ranking table into the NAS process. This table enables efficient hardware-software co-optimisation by eliminating the need for repetitive network evaluations, thereby accelerating the search for optimal architectures under hardware constraints. To enable cycle-accurate and platform-specific evaluation on Binary Neural Network (BNN), we develop LAXOR simulator, a BNN accelerator simulator tailored for on-device inference. LAXOR simulator provides fine-grained performance insights, supporting design decisions for energy-efficient DNN execution. Experiments on standard NAS benchmarks demonstrate that our framework achieves competitive accuracy with faster search times, while providing accurate hardware performance estimation. This dissertation contributes a comprehensive methodology for efficient DNN architecture design and evaluation, bridging the gap between neural architecture search, hardware co-optimisation, and realistic system-level simulation. The proposed techniques pave the way for the rapid deployment of customised and energy-efficient AI systems on resource-constrained platforms.

Tomomasa Yamasaki received his BEng in 2019 and MEng in 2021, both in System Engineering from Aoyama Gakuin University, Tokyo, Japan. He is currently pursuing a PhD in Computer Science at the Singapore University of Technology and Design (SUTD), Singapore. His research interests focus on neural architecture search (NAS), and design automation tools for hardware–software co-optimization. He received the Best Paper Award at the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) in 2023. He was also a recipient of the Best Student Paper Award at the 8th IIAE International Conference on Industrial Application Engineering in 2020.